The hierarchical design-rule checker uses the same rules and techniques as the incremental checker, but it checks all levels of hierarchy below the current cell. To run it, use the Check Hierarchically command (in menu Tool / DRC). To check only a selected subset of the current cell, use Check Selection Area Hierarchically.

After analysis of the circuit, you can review the errors by typing ">" and "<" to step to the next and previous error that was found. You can also see a list of errors in the cell explorer (see Section 4-8).

After a cell has passed Hierarchical DRC with no errors, it is tagged with the current date. In subsequent runs of the Hierarchical DRC, if the cell has not been modified since that date, it is not rechecked. (However, if you change the DRC rules or the technology options, all date information is cleared.) If you wish to force all cells to be rechecked, use the "Clear valid DRC dates" button in the "DRC" preferences (in menu File / Preferences..., "Tools" section, "DRC" tab). To see which cells have passed Hierarchical DRC, use the General Cell Lists... command (in menu Cell / Cell Info) A "D" is shown in on the right for cells that are DRC current (see Section 3-7-1).

There are three levels of checking that can be requested in the "DRC" preferences, each consuming more time and finding more errors.

- "Report just 1 error per cell" tells the system to stop checking a cell after the first error has been found. By using this option, you can more quickly determine which cells in the design are correct, without knowing exactly where the errors lie. Then, you can go to the cells with errors and do a more complete check.
- "Report just 1 error per node or arc" is the default. It stops checking a node or arc when it has found any design rule violation.
- "Report all errors" tells the system to continue checking a node or arc, even if an error has been found. This will report all violations found, but can take more time.