The Bus arc of the Schematics technology is a special arc that can carry multiple signals. When giving a network name to Bus arcs, it is possible to specify complex bus names. Bus names can be lists (for example, "clock,in1,out" which aggregates 3 singals into a 3-wide bus) or they can be arrays (for example, "A[0:7]" which defines an 8-wide bus). Arrays indexes can be individual values, or ranges of values (for example, the bus "b[0],c[3,5],d[1:2],e[8:6]" is an 8-wide bus with signals in this order: b[0], c[3], c[5], d[1], d[2], e[8], e[7], e[6]). Finally, it is possible to use symbolic indices in bus naming (for example, the bus "r[x,y]" defines a 2-wide bus with the signals r[x] and r[y]).

When a bus is unnamed, the system determines its width from the ports that it connects. Some tools (such as simulation netlisters) need to name everything, and so use automatically-generated names.

Individual wires that connect to a bus must be named with names from that bus. As an aid in obtaining individual signals from a bus, the Rip Bus command (in menu Edit / Arc) will automatically create such wires for the selected bus arc.

Besides using array names on busses, you can also give array names to schematic nodes. Netlisters will create multiple copies of that node, named with the individual elements of the array.