Before generating Verilog decks, it is possible to annotate circuits with additional Verilog declarations and code that will be included in the deck. To add Verilog code, select "Verilog Code" under the "Misc." entry in the component palette. To add a Verilog declaration, select "Verilog Declaration" under the "Misc." entry in the component palette. These pieces of text can be manipulated like any other text object (see Section 6-8-1 on text).

Additional control of Verilog deck generation is accomplished with the "Verilog" preferences (in menu File / Preferences..., "Tools" section, "Verilog" tab). A checkbox lets you choose whether or not to use the Verilog "assign" construct. You can control the type of Verilog declaration that will be used for wires ("wire" by default, "trireg" if checked). Note that this can be overridden with the Set Verilog Wire command (in menu Tool / Simulation (Verilog) ).

Another properety that can be assigned to transistors is their strength. The Weak command (in menu Tool / Simulation (Verilog) / Transistor Strength) sets the transistor to be weak. The Normal command restores the transistor to be normal strength.

The Verilog preferences dialog also lets you attach disk files with Verilog code to any cell in the library. Once attached, the generated Verilog will use the contents of that file instead of examining the cell contents. This allows you to create your own definitions in situations where the derived Verilog would be too complex or otherwise incorrect. For an example of Verilog layout and code, look at the cell "tool-SimulateVERILOG" in the Samples library (get this library with the Load Samples Library command, in menu Help).