A technology is an environment in which design is done. Technologies can be layout specific, for example MOSIS CMOS, or they can be abstract, for example Schematics and Artwork. There are multiple CMOS variations to handle popular design rules such as MOSIS, submicron, etc.

Electric has a "sample" library built into it that illustrates many features. To access it, use the Load Samples Library command (in menu Help). The table below lists the cells in that library which illustrate different technologies:

Cell | Technology | Description
tech-MOSISCMOS | mocmos | MOSIS CMOS rules
tech-nMOS | nmos | n-Channel MOS rules
tech-SchematicsDigital | schematics | Digital schematics layout
tech-SchematicsAnalog | schematics | Analog schematics layout
tech-Artwork | artwork | Graphical design

Electric makes no restrictions about mixing components from different technologies. While editing a cell, you can switch technologies and start using new components along side the ones from the former technology. It is up to the designer to ensure that the resulting circuit is sensible.

Each technology consists of a set of primitive nodes and arcs. These, in turn, are constructed from one or more layers. Each technology also includes information necessary to do design, such as design rules, connectivity rules, simulation attributes, etc.

Within a technology, there are three classes of primitive nodes: pins, components, and pure-layer nodes. The pins are used to join arcs, so there is one pin for every arc in the technology. The components are the basic nodes used in design: contacts, transistors, etc. Finally, the pure-layer nodes are used for geometric manipulation, so there is one for every layer in the technology.

The component menu on the left side of the editing window contains arcs at the bottom (the menu entries with red borders), pin nodes above that (these appear as boxes with a cross inside), and components after that (the more complex layer combinations). The pure-layer nodes are available under the entry labeled "Pure" (see Section 6-10-1).